1. Field of the Invention
This invention relates to an inner-layer heat-dissipating board, a multi-chip stack package structure having the inner-layer heat-dissipating board and a fabrication method thereof, and, more particularly, to a multi-chip stack package structure that provides a heat-dissipating path and increases the overall structural rigidity in an stacked structure and a fabrication method thereof.
2. Description of Related Art
With the rapid development of technology, a variety of novel products constantly come to the market. These products are designed to be increasingly low-profiled and compact sized, so as to meet the consumers' demands for ease of use and portability.
In addition to the characteristics of being low-profile and compact in size, modern electronic products are preferred to have high efficiency, low power consumption and high functionality as well. Accordingly, manufactures have developed a technique to dispose a plurality of semiconductor chips on a circuit board or a packing substrate, in order to increase the electrical functionality. However, only a limited number of semiconductor chips can be disposed on a single packaging substrate, in that the packaging substrate does not have a large enough area. Moreover, the planer disposition of the semiconductor chips on the packaging substrate is contradictory to the requirements of having a low-profile and compact size. To address this problem, a package structure has been designed to have a plurality of semiconductor chips stacked on one another. Such a package structure having the semiconductor chips stacked has a short transmission path, and characteristics of high efficiency, low power consumption and high functionality. Compared to the conventional package structure in which a plurality of semiconductor chips are disposed on a packaging substrate one by one, the package structure in which the semiconductor chips are stacked on one another may dramatically reduce the area of the packaging substrate.
Referring to FIG. 1, a multi-chip stack package structure is shown according to the prior art. A first semiconductor chip 11 is electrically connected through solder balls 110 to a packaging substrate 10. A second semiconductor chip 12 is stacked on the first semiconductor chip 11. A third semiconductor chip 13 is stacked on the second semiconductor chip 12. The second semiconductor chip 12, and the third semiconductor chip 13 are electrically connected to the packaging substrate 10 by solder wires 14 in a wire bonding manner.
However, the second semiconductor chip 12 has to be smaller than the first semiconductor chip 11 and the third semiconductor chip 13 also has to be smaller than the second semiconductor chip 12, such that the first and second semiconductor chips 11 and 12 may provide an area on top for the solder wires 14 to be bonded thereon. As a result, a limited number of semiconductor chips may be installed on the packaging substrate. On the other hand, the solder wires 14 are in the shape of an arc, which also limits the reduction of the volume of the package structure.
In order to solve the problems, enhance the electrical functionality and transmission efficiency, and meet the trends toward functional integration, semiconductor manufacturers have developed a technique that vertically stack on a packaging substrate a plurality of semiconductor chips each of which has through-silicon vias (TSVs) in which a conductive material is filled, to constitute a semiconductor package structure. The semiconductor package structure not only has good electrical functionality and enhanced electrical transmission efficiency, but can also meet the demands of high-end electronic products.
Referring to FIG. 2A, a multi-chip stack package structure with TSVs is shown. A plurality of TSV chips 21 are stacked on and electrically connected to a packaging substrate 20 by solder balls 201. A semiconductor chip 22 is disposed on the very top one of the TSV chips 21.
However, heat generated by the TSV chips 21, particularly those disposed in the middle of the stack, is difficult to dissipate to a region outside of the stack, since the gaps between any two adjacent ones of the TSV chips 21 are very small. If the temperature goes too high, it may severely impact the operation of the TSV chips 21, or even damage the TSV chips 21.
To address the above problem, a metal heat-dissipating sheet 23 is further adhered to a surface of the semiconductor chip 22 that is exposed to air, as shown in FIG. 2B. As a result, heat generated by the TSV chips 21 disposed in the middle of the stack may be dissipated through a conductive material such as the solder balls 201 and the TSVs to the metal heat-dissipating sheet 23.
However, heat generated by the TSV chips 21 in the middle of the stack needs to travel a long path to arrive at the metal heat-dissipating sheet 23, which reduces the heat-dissipating efficiency. Moreover, the metal heat-dissipating sheet 23 that is disposed on the semiconductor chip 22 should not have an area much greater than that of the semiconductor chip 22, or adherence and stress problems may occur, and the semiconductor chip 22 may be easily broken.
Therefore, finding a way to provide an inner layer heat-dissipating board, a multi-chip stack package structure having the inner layer heat-dissipating board and fabrication method thereof is becoming one of the most popular issues in the art.